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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:05:46 03/04/2012 
-- Design Name: 
-- Module Name:    InterruptREG - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InterruptREG is
    Port ( clk : in  STD_LOGIC;
			  pc_in : in  STD_LOGIC_VECTOR (9 downto 0);
           ZF : in  STD_LOGIC;
           CF : in  STD_LOGIC;
           interrupt_read : in  STD_LOGIC;
           interrupt_store : in  STD_LOGIC;
           pc_out : out  STD_LOGIC_VECTOR (9 downto 0);
           int_ZF : out  STD_LOGIC;
           int_CF : out  STD_LOGIC);
end InterruptREG;

architecture Behavioral of InterruptREG is
	
begin
	process(clk)
	begin
		if(rising_edge(clk)) then 
			if(interrupt_store = '1') then --La control unit nos escribe los flags
				pc_out <= pc_in;
		      int_ZF <= ZF;
		      int_CF <= CF;
			end if;
		end if;
		
		
	end process;
end Behavioral;
